Crystal symmetry in sapphire and many other single crystal systems in the past could not be determined by the unaided eye. In certain situations, crystal symmetry considerations result in anisotropic behavior of the crystal structure necessitating specific crystalline orientations be maintained in reference to the overall geometry of the end device or part. Currently, there are available a wide variety of methods to mark a wafer made of semiconductor, sapphire, or other materials. In reviewing the prior art, several different methods of marking wafers to determine the crystalline orientation were disclosed. These methods include: using various orientation flats and notches, marking the surface of the wafer with an identifying mark using a laser beam, marking a beveled edge portion with a bar code, adding a beveled portion which aids differentiating between the top and bottom, removing the corner of a rectangular wafer, and utilizing systems having a notch and a hole to align a wafer.
A number of methods discuss altering the wafers with various types of marks. The Guldi U.S. Pat. App. Pub. No. 2002/153,620 discloses a system of marking either the surface or bevel edge of a semiconductor with a laser to form a marking such as a two-dimensional bar code along the wafer edge at specified angular positions. The Choi U.S. Pat. App. Pub. No. 2004/124,502 discloses a semiconductor wafer having a marking region on a lower side surface of a convex edge of the wafer wherein the marking may be carved by a laser. The Yamaguchi U.S. Pat. No. 4,630,093 discloses adding asymmetry to semiconductor wafers belonging to groups III-V having crystalline structure of the zinc blend type by providing asymmetry on the peripheral edge with regard to the middle plane. The disclosure further explains that when a wafer is etched, the etching process is either slowed down or sped up according to whether the surface is mesa or reverse mesa. The Arikado U.S. Pub. No. 2003/3,608 A1 discloses a semiconductor wafer having a beveled contour on its outer periphery and an ID mark is provided on the beveled contour. The Sakaguchi U.S. Pat. Pub. No. 2001/38,153 discloses the use of a wafer having a semiconductor layer which forms a supporting substrate and an insulating layer therebetween whereby a mark is formed in an areas other than upon the semiconductor layer.
The Tan U.S. Pat. Pub. No. 2001/1,077 discloses a method for producing an alignment mark on only the oxide or BPSG layer of a wafer. The Arai U.S. Pat. Pub. No. 2004/89,958 A1 discloses a semiconductor wafer having an ID mark formed consisting of a bar code or the like which is positioned on the interior of a base plate. The Guldi U.S. Pat. Pub. No. 2004/4,361 A1 discloses a marking for semiconductor wafers which includes information such as a 2D bar code that is marked with a laser on several locations on the wafer so that these edge markings may be used for visual orientation.
The Shikatanki U.S. Pat. No. 4,632,884 discloses a rectangular semiconductor wafer having either a corner cut off or a V-shaped groove located along its edge to identify the front and back sides of the wafer. The Nakayama U.S. Pat. No. 6,909,165 B2 discloses a rectangular nitride semiconductor wafer which has a longer slanting edge and a shorter slanting edge at neighboring corners. The Yasue U.S. Pat. No. 5,060,043 discloses a semiconductor wafer having angular perimeter notching to disclose crystal orientation. The notches are small so that they may be formed on the bar member prior to slicing. The Yasue U.S. Pat. No. 5,147,824 discloses a method of manufacturing a wafer having angular notches to disclose crystal orientation.
The Kimura U.S. Pat. No. 5,876,819 disclose the use of a semicircular contour which is utilized as mark for detecting orientation of the wafer in lieu of a traditional semicircular cut out. This decreases both strength and uniformity of thickness in the area of the cutout. The Lee U.S. Pat. No. 5,800,906 discloses a wafer label which includes concave marks formed on the edge of a flat zone of the wafer via use of photolithography or laser etching in a conventional manner. The Miyashita U.S. Pat. No. 5,439,723 discloses a semiconductor wafer which uses an angular notch and an aperture to achieve precision alignment along an orientation flat.
The Jang U.S. Pat. No. 5,956,596 discloses a round semiconductor wafer having a flat zone and a rectangular bar code region for marking wafers. The Oishi U.S. Pat. No. 5,993,292 discloses a method of producing a wafer without a notch that has a mark oriented to a notch provided earlier during processing. Similarly, the Oishi U.S. Pat. No. 6,004,405 discloses a wafer having laser marks carved as a bar code upon a chamfered edge. The Jantke U.S. Pat. No. 6,177,285 B1 discloses a method for determining crystal orientation by finding the distance between adjacent mask openings having a double T-shape. This method allows orientation to be determined even by the naked eye.
The Chen U.S. Pat. No. 6,235,637 B1 discloses a method of marking a semiconductor layer using laser scribing which will not induce flat edge particle yield reduction or edge defects. The Ipposhi U.S. Pat. No. 6,864,534 B1 discloses two types of semiconductor wafers having a notch or an orientation flat. The Arai U.S. Pat. No. 6,967,416 discloses a wafer support surface having a crystal orientation angular notch provided along its outer periphery wherein the orientation of a wafer may be determined even when its outer edge has been chipped. The Arikado U.S. Pat. No. 7,057,259 B2 discloses a semiconductor wafer having a bevel contour and an ID mark formed on the to bevel contour. (See the Arikado disclosure, infra). The Hikada U.S. Pat. No. 7,102,206 B2 discloses a semiconductor wafer with a substrate and a method for producing that semiconductor wherein the semiconductor has a notch and an curved portion wherein the difference in curvature between the two shoulder portions on the notice is between 0.0 mm and 0.1 mm.
Still other patents disclose various systems of alignment marks used on different types of wafers. The Bijnen U.S. Pat. App. Pub. No. 2007/313,743 discloses a lithographic substrate having a plurality of alignment marks which provide features spaced apart at different distances. The Roman U.S. Pat. No. 5,580,831 discloses a method for producing alignment marks on opposing surfaces of a flat surface, such as a semiconductor wafer. In this process, symmetrical cuts and grooves are disposed upon the surface of a wafer. Cuts being made on opposing surfaces of the wafer are slightly offset to lessen the risk of mechanical failure occurring. The Yao U.S. Pat Pub. No. 2001/33,033 discloses an alignment mark configuration wherein the alignment mark is protected from subsequent planarization using a plurality of rectangular recesses. The Ouellet U.S. Pat. Pub. No. U.S. 2003/332,299 A1 discloses a method for aligning structures on the first and second sides of a wafer using transparent islets and alignment marks.
The Inoue reference, U.S. Pat. No. 5,182,233 discloses the use of a compound semiconductor pellet wherein the major surface of the pellet and the side surfaces thereof are both 100 planes and an off center aperture is utilized to induce asymmetry into the configuration of the wafer. The Teramoto U.S. Pat. Pub. No. 2003/102,576 A1 discloses an alignment pattern and method of forming the pattern having a sloped surface, an alignment hole, an insulation layer, and an oxide film for the purpose of patterning a metal interconnection film. The Ido US. Pat. Pub. No. 2004/262,783 A1 discloses semiconductor devices having alignments mark and imbedded portions on the surface of a wafer. The wafer surface is also provided with a high reflectance portion and a low reflectance portion, and an irregular reflection film arranged internally.
The Berge U.S. Pat. Pub. No. 2005/118,781 A1 discloses a method whereby a plurality of alignment markers are anisotropically etched into the substrate of a wafer in order to determine the orientation of the crystal axis. The Kobayashi U.S. Pat. Pub. No. 2005/70,068 A1 discloses a method of forming an alignment mark on a substrate by removing a portion of material in a grid like etching on the surface of a wafer. The Lin U.S. Pat. No. 5,982,044 discloses an alignment pattern and algorithm for producing the marks, which minimize misalignment due to asymmetric formation of a material layer. The pattern consists of a substantially circular grid and triangular etchings which are photomasked upon the wafer.
The So U.S. Pat. No. 6,261,918 B1 discloses a method of producing alignment marks in an integrated circuit by forming a basic alignment mark, and then creating a second set of marks overlapping the first set of marks which are positioned perpendicular thereto to form a preservation pattern and then further etching to produce a checkerboard type pattern. The wafer then undergoes CMP (Chemical Mechanical Planarization) without damaging the first set of marks. The Glenn U.S. Pat. No. 6,869,861 B1 discloses a vertical and horizontal scribe line that aids in backside alignment of the wafer. An aperture may be drilled through the wafer at the intersection of the scribe lines.
The Bijnen disclosure, U.S. Pat. Pub. No. 2007/31,743 discloses the use of a lithographic substrate to provide an alignment mark having a plurality of features spaced apart from one another by varying distances. The Pike U.S. Pat. No. 6,410,927 B1 discloses a semiconductor wafer analysis tool for scanning raw wafers which helps orient and align wafers to a preexisting mark, which aids in the identification of defects prior to further processing of the wafer. The Witvrouw U.S. Pat. No. 6,740,542 B2 discloses a method for producing micromachined devices wherein a crystalline wafer is processed to align it in the direction that a cleavage is likely to occur in order to provide improved resistance to crack propagation. An etching or grid is used in this instance.
Others devices found in prior art have rounded edges, but the primary purpose of such a rounded edge is to prevent chipping rather than to impart asymmetry to a substrate. The Mejima U.S. Pat. No. 4,783,225 discloses a wafer having chamfered bent portions in the joint regions and a semicircular notch, which bent portions prevent chipping of the wafer edge; the wafer is used for creating integrated circuits. The Maejima U.S. Pat. No. 5,230,747 discloses a semiconductor wafer having chamfered bent portions in joint regions and a cutaway portion, such as an orientation flat. Acute bends are formed in the joint parts between the flat portion of the wafer and its contour to prevent chipping away at the joint portion. The Ogino U.S. Pat. No. 5,110,764 discloses a substantially rectangular semiconductor silicon wafer having a beveled portion asymmetrically formed which prevents its circumferential edges from being chipped. Similarly, the Ogino U.S. Pat. No. 5,021,862 discloses an asymmetrical circumferential edge beveled semiconductor wafer which prevents the wafer from being chipped. The Kimura U.S. Pat. No. 5,045,505 discloses a method of processing a semiconductor device by simultaneously forming annular beveled portions on both the front and back of a wafer in order to prevent the edge of the wafer from chipping because the grinding operation is balanced, having equal pressure being applied to both front and back surfaces.
The Maejima U.S. Pat. No. 5,279,992 discloses a wafer having a curved notch along its outer periphery and chamfered portions to prevent chipping of the wafer edge. The Nishi U.S. Pat. No. 6,302,769 B1 discloses a method of chamfering a disk-shaped wafer using a grindstone to first make an angular notch in the edge, and then the grindstone makes a semicircular edge chamfer both in the interior of the notch, and also along the entire perimeter of the wafer. The Asano U.S. Pat. No. 6,897,126 B2 discloses a method of manufacturing a compound semiconductor device which is given a slanted edge to reduce chipping when a wafer is diced along an angle between 30 and 60 degrees with respect to the orientation flat.
Finally, many publications disclose several other ways to alter semiconductor wafers. For example, the Urakami U.S. Pub. No. 2001/48,142 discloses a semiconductor substrate and method for developing a trench in that substrate upon the surface of the wafer. Similarly, the Urakami U.S. Pat. App. Pub. No. 2003/164,534 discloses a semiconductor substrate and method for developing a trench in that substrate. See the related Urakami disclosure, infra. The Fukuda U.S. Pat. App. Pub. No. 2004/97,084 A1 discloses a method for grinding the rear surface of a semiconductor to a flat surface and predetermined thickness. In one embodiment, a sharp knife edge is formed.
The Tomita U.S. Pat. App. Pub. No. 2004/246,795 discloses a method of cutting wafers using a large wafer and a small wafer moving together via means of a pusher plate so that the larger wafer and the smaller wafer may be bonded to one another with their centerlines and orientation flats properly aligned. The Subramanian U.S. Pat. App. Pub. No. 2006/118,920 A1 discloses a method for forming vias that have at least one pair of opposing side walls using potassium hydroxide.
The Arai U.S. Pat. No. 7,183,178 B2 discloses a method of manufacturing a semiconductor wafer wherein a film is formed on the wafer to prevent it from warping during the subsequent grinding steps. The Fournel U.S. Pat. Pub. No. 2003/175,531 A1 discloses a process for controlling the formation of secondary structures on the surface of a crystalline structure. The Arai U.S. Pat. Pub. No. 2005/106,840 A1 discloses a method of forming a semiconductor wafer wherein a film is applied to the back surface to prevent it from warping. See the Arai reference U.S. Pat. No. 7,183,178, supra.
The Doris U.S. Pat. Pub. No. 2005/280,121 A1 discloses a hybrid substrate and a method for fabricating such a substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs). The van den Brekel U.S. Pat. No. 4,000,019 discloses a method of manufacturing a semiconductor device having a pattern of highly doped zones as well as providing an epitaxial silicon layer on one side. The Nishimura U.S. Pat. No. 4,861,418 discloses a method of manufacturing a semiconductor crystalline layer wherein a polycrystalline layer is formed, then an insulating layer is formed, and finally an argonne laser beam scans the layers to form a single crystalline layer on the wafer from the underlying semiconductor crystals which are used as the seeds. The Maruyama U.S. Pat. No. 5,751,005 discloses a semiconductor substrate having a chamfer produced by vapor phase epitaxial growth in order to locate an edge crown. The Bruel U.S. Reissue Pat. No. RE39,484 E discloses a process for the preparation of a semiconductor film.
For certain current substrate applications, the standard methods for marking substrates, and which methods are recommended by industry standards such as SEMI, are not acceptable or desirable. A specific example occurs when sapphire substrates are used in silicon-on-sapphire applications. The tooling used for silicon deposition and resultant wafer handling do not typically accept the number of orientation flats required to visually maintain crystal orientation. A non-standard method must be employed. The inventive asymmetrical wafer configurations and method for making same presented herein consists of rounding at least one corner of a single orientation flat to impart visual and tactile asymmetry and accordingly they constitute a vast improvement over the prior art.
Nowhere in the prior is found a substantially annular wafer having at least one truncated flat whereby at least one corner has been rounded in order to facilitate differentiation between the two sides of the wafer. Also, nothing may be found in the prior art wherein a substantially circular wafer which has a notch having at least one rounded corner wherein the configuration creates visual and tactile asymmetry in order to determine the wafer's crystalline orientation. Because the present inventive configuration of wafers is completely novel in the art, the preferred methods employed to create such new products are likewise novel.